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* refactor(uavcan): base the libuavcan clock on HRT instead of a dedicated timer The stm32, stm32h7 and kinetis drivers each ran a 16-bit hardware timer with a software overflow extension, a second copy of what HRT provides, and slewed UTC by patching that accumulator from the timer interrupt. Every CAN board paid a general-purpose timer for it, and the bus time base led HRT by the timer phase at seeding even when the FC is the sync master. Monotonic time is now hrt_absolute_time() and UTC is HRT plus an offset that time sync moves. Each adjustment is applied directly; the rate PID and its lock accessors had no callers, and at the sub-100 us errors sync produces after convergence a 1 Hz offset correction bounds the error to crystal drift over one second. The timer number plumbing and the BOARD_UAVCAN_TIMER_OVERRIDE option go with it. * refactor(uavcan): drop the vestigial clock::init and the timer enables it left behind With the hardware timer gone, init() only set a flag, so the flag is set where the singleton is constructed. The three boards that enabled their override timer in defconfig alongside the override no longer need it.