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84ddad88e3
A seq_cst px4::atomic emits a hardware `dmb` on ARM. That barrier only orders accesses as seen by a second observer (another CPU core or DMA); for inter-thread synchronisation on a single-core (uniprocessor) target there is no second core, so the `dmb` is dead weight - only the compiler ordering is required. On a NuttX build without CONFIG_SMP, keep full seq_cst semantics but emit a compiler-only fence (__atomic_signal_fence, zero instructions) instead of the `dmb`. This mirrors Linux, where smp_mb()/smp_rmb()/smp_wmb() collapse to a compiler barrier on uniprocessor builds. SMP NuttX and POSIX are unchanged (real barriers, so SITL under ThreadSanitizer keeps full ordering). 64-bit types (not lock-free on a 32-bit core) keep the existing interrupts-off critical section, which already provides both atomicity and ordering. The public API is unchanged - no per-call ordering knob. Verified on arm-none-eabi Cortex-M7 that the single-core path emits no `dmb` while keeping atomicity, and that SMP/POSIX is unchanged: load (single-core): ldr (signal_fence: 0 instr) store (single-core): str fadd (single-core): ldrex/strex loop, no dmb load (seq_cst/SMP): dmb ish; ldr; dmb ish store (seq_cst/SMP): dmb ish; str; dmb ish fadd (seq_cst/SMP): dmb ish; ldrex/strex; dmb ish Shrinks fmu-v6x by ~2.8 KB (dead barriers removed from atomics already in use), with no behaviour change. Note: inter-thread ordering only - DMA/device sync still needs explicit barriers.